SH7055S Datasheet, PDF (199/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Bit: 31
30
29
28
27
26
25
24
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
…
…
Initial value: —
—
—
…
R/W: R/W R/W R/W
…
…
2
1
0
…
…
—
—
—
…
R/W R/W R/W
10.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)
DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit readable/writable registers that
specify the destination address of a DMA transfer. These registers have a count function, and
during a DMA transfer, they indicate the next destination address.
Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when
performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set.
The value after a power-on reset and in standby mode is undefined.
Bit: 31
30
29
28
27
26
25
24
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
…
…
Initial value: —
—
—
…
R/W: R/W R/W R/W
…
…
2
1
0
…
…
—
—
—
…
R/W R/W R/W
10.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)
DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 24-bit read/write registers that
specify the transfer count for the channel (byte count, word count, or longword count) in bits 23 to
0. Specifying H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting,
16,777,216 transfers. During DMAC operation, these registers indicate the remaining number of
transfers.
The upper 8 bits of DMATCR always read 0. The write value, also, should always be 0.
Rev.2.0, 07/03, page 161 of 960