SH7055S Datasheet, PDF (378/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Correction Counter 10E (TCNT10E): Correction counter 10E (TCNT10E) is a 16-bit
readable/writable register that loads the TCNT10D shift value at the external input (TI10) timing,
and counts on the multiplied clock (AGCK1) output by reload counter 10C (TCNT10C).
However, if CCS in timer I/O control register 10 (TIOR10) is set to 1, when the TCNT10D shifted
value is reached the count is halted.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNT10E can only be accessed by a word read or write.
TCNT10E is initialized to H'0000 by a power-on reset, and in hardware standby mode and
software standby mode.
Correction Counter 10F (TCNT10F): Correction counter 10F (TCNT10F) is a 16-bit
readable/writable register that counts up on Pφ clock cycles if the counter value is smaller than the
correction counter 10E (TCNT10E) value when the STR10 bit in TSTR1 has been set for counter
operation. The count is halted by a match with the correction counter clear register (TCCLR10). If
TI10 is input when TCNT10D = H'00, TCNT10F is initialized and correction is carried out. When
TCNT10F = TCCLR10, TCNT10F is cleared to H'0001. While TCNT10F ≠ TCCLR10,
TCNT10F is incremented automatically until it reaches the TCCLR10 value, and is then cleared to
H'0001.
A corrected clock (AGCKM) is output following correction each time this counter is incremented.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNT10F is can only be accessed by a word read or write.
TCNT10F is initialized to H'0001 by a power-on reset, and in hardware standby mode and
software standby mode.
Rev.2.0, 07/03, page 340 of 960