SH7055S Datasheet, PDF (385/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 3—Reserved: This bit always reads 0. The write value should always be 0.
• Bits 2 to 0—I/O Control 10G2 to 10G0 (IO10G2 to IO10G0): These bits select the function of
general register 10G (GR10G).
Bit 2:
IO10G2
0
Bit 1:
IO10G1
0
1
1
*
*: Donít care
Bit 0:
IO10G0
0
1
*
*
Description
GR is an output
compare register
Cannot be used
Compare-match disabled (Initial value)
GR10G = TCNT10G compare-match
Cannot be used
Timer Control Register 10 (TCR10): TCR10 is an 8-bit readable/writable register that selects
the correction counter clear register (TCCLR10) compare-match counter clear source, enables or
disables the noise canceler function, and selects the external input (TI10) edge.
TCR10 is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Bit:
7
6
5
4
3
TRG2BEN TRG1BEN TRG2AEN TRG1AEN TRG0DEN
Initial value:
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
2
NCE
0
R/W
1
CKEG1
0
R/W
0
CKEG0
0
R/W
• Bit 7—Trigger 2B Enable (TRG2BEN): Enables or disables counter clearing for channel 2
TCNT2B. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT2B
count clock. If TCNT2B counts while clearing is enabled, TCNT2B will be cleared.
Bit 7: TRG2BEN
0
1
Description
Channel 2 counter B (TCNT2B) clearing when correction counter clear
register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value)
Channel 2 counter B (TCNT2B) clearing when correction counter clear
register (TCCLR10) = correction counter (TCNT10F) is enabled
Rev.2.0, 07/03, page 347 of 960