SH7055S Datasheet, PDF (26/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

8.2.3 User Break Bus Cycle Register (UBBR) ............................................................. 124
8.2.4 User Break Control Register (UBCR).................................................................. 126
8.3 Operation .......................................................................................................................... 127
8.3.1 Flow of the User Break Operation ....................................................................... 127
8.3.2 Break on On-Chip Memory Instruction Fetch Cycle........................................... 129
8.3.3 Program Counter (PC) Values Saved................................................................... 129
8.4 Examples of Use ............................................................................................................... 129
8.4.1 Break on CPU Instruction Fetch Cycle................................................................ 129
8.4.2 Break on CPU Data Access Cycle ....................................................................... 130
8.4.3 Break on DMA Cycle .......................................................................................... 131
8.5 Usage Notes ...................................................................................................................... 131
8.5.1 Simultaneous Fetching of Two Instructions ........................................................ 131
8.5.2 Instruction Fetches at Branches ........................................................................... 131
8.5.3 Contention between User Break and Exception Processing ................................ 132
8.5.4 Break at Non-Delay Branch Instruction Jump Destination.................................. 132
8.5.5 User Break Trigger Output .................................................................................. 133
8.5.6 Module Standby................................................................................................... 133
Section 9 Bus State Controller (BSC) ...............................................................135
9.1 Overview........................................................................................................................... 135
9.1.1 Features................................................................................................................ 135
9.1.2 Block Diagram ..................................................................................................... 136
9.1.3 Pin Configuration................................................................................................. 137
9.1.4 Register Configuration......................................................................................... 137
9.1.5 Address Map ........................................................................................................ 138
9.2 Description of Registers.................................................................................................... 140
9.2.1 Bus Control Register 1 (BCR1) ........................................................................... 140
9.2.2 Bus Control Register 2 (BCR2) ........................................................................... 141
9.2.3 Wait Control Register (WCR).............................................................................. 145
9.2.4 RAM Emulation Register (RAMER)................................................................... 146
9.3 Accessing External Space ................................................................................................. 148
9.3.1 Basic Timing........................................................................................................ 148
9.3.2 Wait State Control................................................................................................ 149
9.3.3 CS Assert Period Extension ................................................................................. 151
9.4 Waits between Access Cycles ........................................................................................... 152
9.4.1 Prevention of Data Bus Conflicts......................................................................... 152
9.4.2 Simplification of Bus Cycle Start Detection ........................................................ 153
9.5 Bus Arbitration.................................................................................................................. 154
9.6 Memory Connection Examples......................................................................................... 155
Section 10 Direct Memory Access Controller (DMAC) ...................................157
10.1 Overview........................................................................................................................... 157
10.1.1 Features................................................................................................................ 157
Rev.2.0, 07/03, page xxvi of xxxviii