SH7055S Datasheet, PDF(407/1002 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SH7055S Datasheet, PDF (407/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

◁

after setting H'FFFF in the cycle register, the cycle registerâs compare-match flag and overflow

flag will be set simultaneously.

Note that 0% or 100% duty output is not possible in channel 3 to 5 PWM mode.

An example of channel 3 to 5 PWM mode operation is shown in figure 11.23.

In the example in figure 11.23, H'0008 is set in GR3D, H'0002 is set in GR3A, GR3B, and GR3C,

and channel 3 is activated; then, during operation, H'0000 is set in GR3A, GR3B, and GR3C, and

output is performed to external pins TIOA3 to TIOC3. Note that 0% duty output is not possible

even though H'0000 is set.

PÃ¸

TCNT3

Clock

TCNT3 0008

0000

0001

0002

0003

0007

0008

0000

0001

0002

0003

0004

0005

GR3D

GR3Aâ3C

(pulse width)

TIO3Aâ

TIO3C

TSR3

0008

0002

0008

Rewritten by software

0000

Cleared by software

Cleared by software

Figure 11.23 Channel 3 to 5 PWM Mode Operation

11.3.11 Event Count Function and Event Cycle Measurement

Channel 9 has six 8-bit event counters (ECNT9A to ECNT9F) and corresponding general registers

(GR9A to GR9F). Each event counter has an external pin (TI9A to TI9F).

Each ECNT9 operates unconditionally as an event counter. When an edge is input from the

external pin, ECNT9 is incremented. When ECNT9 matches the value set in GR9, it is cleared,

and then counts up when an edge is again input at the external pin. By making the appropriate

setting in the interrupt enable register (TIER) beforehand, an interrupt request can be sent to the

CPU on compare-match.

For ECNT9A to ECNT9D, a trigger can be transmitted to channel 3 when a compare-match

occurs. In channel 3, if the channel 9 trigger input is set in the timer I/O control register (TIOR)

and the corresponding bit is set to 1 in the timer start register (TSTR), the TCNT3 value is

captured in the corresponding general register (GR3A to GR3D) when an ECNT9A to ECNT9D

compare-match occurs. This enables the event cycle to be measured.

Rev.2.0, 07/03, page 369 of 960

▷