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SH7055S Datasheet, PDF (921/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series
26.3.3 Control Signal Timing
Table 26.8 shows control signal timing.
Table 26.8 Control Signal Timing
Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC,
VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C.
When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1.
When writing or erasing on-chip flash memory, Ta = –40°C to 85°C.
Item
Symbol Min
RES pulse width
t
20
RESW
RES setup time
t
40
RESS
MD2–MD0 setup time
tMDS
20
NMI setup time
tNMIS
24
IRQ7–IRQ0 setup time*1 (edge detection) tIRQES
24
IRQ7–IRQ0 setup time*1 (level detection)
t
IRQLS
24
NMI hold time
t
24
NMIH
IRQ7–IRQ0 hold time
t
24
IRQEH
IRQOUT output delay time
tIRQOD
—
Bus request setup time
tBRQS
24
Bus acknowledge delay time 1
t
—
BACKD1
Bus acknowledge delay time 2
t
—
BACKD2
Bus three-state delay time
t
—
BZD
Max
—
—
—
—
—
—
—
—
100
—
30
30
30
Unit
t
cyc
ns
tcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figures
Figure 26.5
Figure 26.6
Figure 26.7
Figure 26.8*2
[Operating precautions]
*1 The RES, NMI, and IRQ7–IRQ0 signals are asynchronous inputs, but when the setup times
shown here are provided, the signals are considered to have been changed at clock fall. If the
setup times are not provided, recognition is delayed until the next clock rise or fall.
*2 The guaranteed operating range of power supply PVCC1 in the MCU expanded modes is only
PVCC1 = 3.3 V ±0.3 V. Do not use a voltage outside this range.
Rev.2.0, 07/03, page 883 of 960