SH7055S Datasheet, PDF (112/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

5.1.2 Pin Configuration
The pins relating to the clock pulse generator are shown in table 5.1.
Table 5.1 CPG Pins
Pin Name
External clock
Crystal
System clock
PLL power supply
PLL ground
PLL capacitance
Abbreviation
EXTAL
XTAL
CK
PLLV_CC
PLLV
SS
PLLCAP
I/O
Input
Input
Output
Input
Input
Input
Description
Crystal resonator or external clock input
Crystal resonator connection
System clock output
PLL multiplier circuit power supply
PLL multiplier circuit ground
PLL multiplier circuit oscillation external
capacitance pin
5.2 Frequency Ranges
The input frequency and operating frequency ranges are shown in table 5.2.
Table 5.2 Input Frequency and Operating Frequency
Input Frequency Range
(MHz)
PLL Multiplication Factor
5–10
×4
Note: Crystal resonator and external clock input
Operating Frequency Range
(MHz)
20–40
For the chip operating frequency, a frequency of 4 times the input frequency (EXTAL pin) is
generated as the internal clock (φ) by the on-chip PLL circuit. The system clock (CK pin) output
frequency is the same as that of the internal clock (φ).
Some on-chip peripheral modules operate on a peripheral clock (Pφ) obtained by dividing the
internal clock (φ) by 2. Figure 5.2 shows the relationship between the various clocks. As regards
the system clock, since the input clock is multiplied by the PLL multiplier circuit, the phases of
both clocks are not determined uniformly.
Rev.2.0, 07/03, page 74 of 960