SH7055S Datasheet, PDF (419/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

OVF Setting Timing in Overflow: When TCNT overflows (from H'FFFF to H'0000, or from
H'FFFFFFFF to H'00000000), the OVF bit is set to 1 in the timer status register (TSR).
The timing in this case is shown in figure 11.39.
CK
TCNT input clock
TCNT ^H'FFFF
Overflow signal
H'0000
Interrupt status flag
OVF
Interrupt request signal
OVI
Figure 11.39 OVF Setting Timing in Overflow
Rev.2.0, 07/03, page 381 of 960