SH7055S Datasheet, PDF (273/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Timer Control Registers 9A, 9B, 9C (TCR9A, TCR9B, TCR9C)
TCR9A
Bit:
Initial value:
R/W:
7
6
5
4
— TRG3BEN EGSELB1 EGSELB0
0
0
0
0
R
R/W
R/W
R/W
3
2
1
0
— TRG3AEN EGSELA1 EGSELA0
0
0
0
0
R
R/W
R/W
R/W
TCR9B
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
— TRG3DEN EGSELD1 EGSELD0 — TRG3CEN EGSELC1 EGSELC0
0
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R
R/W
R/W
R/W
TCR9C
Bit:
7
—
Initial value:
0
R/W: R
6
5
4
3
— EGSELF1 EGSELF0 —
0
0
0
0
R
R/W
R/W
R
2
1
0
— EGSELE1 EGSELE0
0
0
0
R
R/W
R/W
• Bit 7—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 6—Trigger Channel 3BEN, 3DEN (TRG3BEN, TRG3DEN): These bits select the channel
9 event counter compare-match signal channel 3 input capture trigger.
Bit 6: TRG3xEN
0
1
x = B or D
Description
Channel 3 input capture trigger in event of channel 9 compare-match
(ECNT9x = GR9x) is disabled
(Initial value)
Channel 3 input capture trigger in event of channel 9 compare-match
(ECNT9x = GR9x) is enabled
Rev.2.0, 07/03, page 235 of 960