SH7055S Datasheet, PDF (401/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

corresponding bit in DSTR is cleared automatically. By making the appropriate setting in the
interrupt enable register (TIER), an interrupt request can be sent to the CPU.
An example of one-shot pulse operation is shown in figure 11.17.
In the example in figure 11.17, H'0005 is set in DCNT and a down-count is started.
Pø
DSTR
DST8A
DCNT
Clock
Synchronized with down-counter clock
TO8A
DCNT8A
0005
0004
TSR8
0003
0002
0001
0000
Cleared by software
Figure 11.17 One-Shot Pulse Output Operation
11.3.6 Offset One-Shot Pulse Function and Output Cutoff Function
By making an appropriate setting in the timer connection register (TCNR), down-counting by
channel 8 down-counters (DCNT8A to DCNT8P) can be started using compare-match signals
from channel 1 general registers (GR1A to GR1H) or channel 1 and 2 compare-match registers
(OCR1, OCR2A to OCR2H). DCNT8A to DCNT8H are connected to channel 1 OCR1 or GR1A
to GR1H, and DCNT8I to DCNT8P are connected to channel 2 OCR2A to OCR2H or GR2A to
GR2H. This enables one-shot pulse output from the external pin (TO8A to TO8P) corresponding
to DCNT. The down-count can be forcibly stopped by making a setting in the one-shot pulse
terminate register (OTR). On channel 1, down-count start or termination by a GR or OCR
compare-match can be selected with the trigger mode register (TRGMDR).
Making a setting in the timer start register (TSTR) starts an up-count by a free-running counter
(TCNT) in channel 1 or 2. When TCNT matches GR or OCR while connection is enabled by
TCNR, the corresponding DSTR is automatically set and DCNT starts counting down. At the
same time, 1 is output from the corresponding external pin (TO8A to TO8P). By making the
appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the
CPU.
When TCNT1 matches GR or OCR, or TCNT2 matches GR, while channel 8 one-shot pulse
termination by a channel 1 or 2 compare-match signal is enabled by OTR, the corresponding
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