SH7055S Datasheet, PDF (528/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

1
Serial
data
Start
bit
0 D0
Parity Stop Start
Data _{bit bit bit}
D1 D7 0/1 1 0 D0
Data
Parity Stop
bit bit
1
D1 D7 0/1 1 ^Idling
(marking)
TDRE
TEND
TXI TXI interrupt
interrupt handler writes
request data in TDR
and clears
TDRE to 0
TXI interrupt
request
1 frame
TEI interrupt request
Figure 15.6 SCI Transmit Operation in Asynchronous Mode
(Example: 8-Bit Data with Parity and One Stop Bit)
Receiving Serial Data (Asynchronous Mode): Figures 15.7 and 15.8 show a sample flowchart
for receiving serial data. The procedure is as follows (the steps correspond to the numbers in the
flowchart).
1. SCI initialization: Set the RxD pin using the PFC.
2. Receive error handling and break detection: If a receive error occurs, read the ORER, PER,
and FER bits of SSR to identify the error. After executing the necessary error handling, clear
ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain set to
1. When a framing error occurs, the RxD pin can be read to detect the break state.
3. SCI status check and receive-data read: Read the serial status register (SSR), check that RDRF
is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.
The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
4. Continue receiving serial data: Read RDR and the RDRF bit and clear RDRF to 0 before the
stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt
(RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary.
Rev.2.0, 07/03, page 490 of 960