SH7055S Datasheet, PDF (180/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

the area specification of the previous access. Refer to section 9.4, Waits between Access
Cycles, for details.
IW31, IW30 specify the idle between cycles for CS3 space; IW21, IW20 specify the idle
between cycles for CS2 space; IW11, IW10 specify the idle between cycles for CS1 space and
IW01, IW00 specify the idle between cycles for CS0 space.
Bit 15: IW31
0
1
Bit 14: IW30
0
1
0
1
Description
No CS3 space idle cycle
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles
(Initial value)
Bit 13: IW21
0
1
Bit 12: IW20
0
1
0
1
Description
No CS2 space idle cycle
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles
(Initial value)
Bit 11: IW11
0
1
Bit 10: IW10
0
1
0
1
Description
No CS1 space idle cycle
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles
(Initial value)
Bit 9: IW01
0
1
Bit 8: IW00
0
1
0
1
Description
No CS0 space idle cycle
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles
(Initial value)
• Bits 7–4—Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The
continuous access idle specification makes insertions to clearly delineate the bus intervals by
once negating the CSn signal when performing consecutive accesses to the same CS space.
When a write immediately follows a read, the number of idle cycles inserted is the larger of the
two values specified by IW and CW. Refer to section 9.4, Waits between Access Cycles, for
details.
Rev.2.0, 07/03, page 142 of 960