SH7055S Datasheet, PDF (677/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

AUDCK
AUDATAn
0000 1110 A3–A0
DIR
Input/output switchover
A31–A28 D3–D0
D31–D28
0000
Not ready
Input
0001
Ready
Output
0001 0001
Ready Ready
Figure 19.6 Example of Write Operation (Longword Write)
AUDCK
AUDATAn
0000 1010 A3–A0
DIR
Input
Input/output switchover
A31–A28
0000
Not ready
0101
Ready
(Bus error)
0101 0101
Ready Ready
(Bus error) (Bus error)
Output
Figure 19.7 Example of Error Occurrence (Longword Read)
19.5 Usage Notes
19.5.1 Initialization
The debugger’s internal buffers and processing states are initialized in the following cases:
1. In a power-on reset
2. In hardware standby mode
3. When AUDRST is driven low
4. When the AUDSRST bit is set to 1 in the SYSCR register (see section 24.2.2)
5. When the MSTOP3 bit is set to 1 in the MSTCR register (see section 24.2.3)
19.5.2 Operation in Software Standby Mode
The debugger is not initialized in software standby mode. However, since the SH7055SF’s
internal operation halts in software standby mode:
1. When AUDMD is high (RAM monitor mode): Ready is not returned. Since the operation after
the software standby mode cancellation is not guaranteed, input AUDRST, and re-execute.
However, when operating on an external clock, the protocol continues.
2. When AUDMD is low (PC trace): Operation stops. However, operation continues when
software standby is released.
Rev.2.0, 07/03, page 639 of 960