SH7055S Datasheet, PDF (803/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter
the error protection state, see section 22.6.3, Error Protection.
Bit 6
MD
0
1
Description
FWE and FLER settings are normal (FWE = 1, FLER = 0)
FWE = 0 or FLER = 1, and erasure cannot be performed
Bit 5—Erasure Execution Error Detect (EE): 1 is returned to this bit when the user MAT could
not be erased or when flash-memory related register settings are partially changed on returning
from the user branch processing.
If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case,
after removing the error factor, erase the user MAT.
If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is
performed. In this case, both the user MAT and user boot MAT are not erased.
Erasure of the user boot MAT must be executed in boot mode or programmer mode.
Bit 5
EE
0
1
Description
Erasure has ended normally
Erasure has ended abnormally (erasure result is not guaranteed)
Bit 4—Flash Key Register Error Detect (FK): Returns the check result of FKEY value before
start of the erasing processing.
Bit 4
FK
0
1
Description
FKEY setting is normal (FKEY = H'5A)
FKEY setting is error (FKEY = value other than H'5A)
Bit 3—Erase Block Select Error Detect (EB): Returns the check result whether the specified
erase-block number is in the block range of the user MAT.
Bit 3
EB
0
1
Description
Setting of erase-block number is normal
Setting of erase-block number is abnormal
Rev.2.0, 07/03, page 765 of 960