SH7055S Datasheet, PDF (804/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Bits 2 and 1—Unused: Return 0.
Bit 0—Success/Fail (SF): Indicates whether the erasing processing has ended normally or not.
Bit 0
SF
0
1
Description
Erasure has ended normally (no error)
Erasure has ended abnormally (error occurs)
22.4.4 RAM Emulation Register (RAMER)
When the realtime programming of the user MAT is emulated, RAMER sets the area of the user
MAT which is overlapped with a part of the on-chip RAM. RAMER is initialized to H'0000 at a
power-on reset or in hardware standby mode and is not initialized in software standby mode. The
RAMER setting must be executed in user mode or in user program mode.
For the division method of the user-MAT area, see table 22.7. In order to operate the emulation
function certainly, the target MAT of the RAM emulation must not be accessed immediately after
RAMER is programmed. If it is accessed, the normal access is not guaranteed.
Bit
: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value _:
0
0
0
0
0
0
0
0
R/W
:
R
R
R
R
R
R
R
R
Bit
:
7
—
Initial value _:
0
R/W
:
R
6
5
—
—
0
0
R
R
4
3
2
1
0
— RAMS RAM2 RAM1 RAM0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
Bits 15 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Rev.2.0, 07/03, page 766 of 960