SH7055S Datasheet, PDF (891/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 1—Module Stop 1 (MSTOP1): Specifies halting of the clock supply to the FPU on-chip
peripheral module. Setting the MSTOP1 bit to 1 stops the clock supply to the FPU.
The MSTOP1 bit cannot be cleared by writing 0 after it has been set to 1. In other words, once
the MSTOP1 bit has been set to 1 and the clock supply to the FPU has been stopped, the clock
supply to the FPU cannot be resumed by clearing the MSTOP1 bit to 0.
An SH7055SF power-on reset is necessary to restart the FPU clock supply after it has been
stopped.
Bit 1: MSTOP1
0
1
Description
FPU operates
Clock supply to FPU stopped
(Initial value)
• Bit 0—Module Stop 0 (MSTOP0): Specifies halting of the clock supply stop to the UBC on-
chip peripheral module.
Clearing the MSTOP0 bit to 0 starts the clock supply to the UBC.
Stopping clock supply to the UBC will reset the internal state of the UBC including its
registers.
Bit 0: MSTOP0
0
1
Description
UBC operates
Clock supply to UBC stopped
(Initial value)
24.2.4 Notes on Register Access
The method of writing to the module standby control register (MSTCR) is different from that of
ordinary registers to prevent inadvertent rewriting.
Be certain to use a word transfer instruction when writing data to MSTCR. Data cannot be written
by a byte transfer instruction. As shown in figure 24.1, set the upper byte to H'3C and transfer data
using the lower byte as write data.
Data can be read by the same method as for ordinary registers.
MSTCR is allocated to address H'FFFFF70A. Always use a byte transfer instruction to read data.
When writing to MSTCR
15
Address: H'FFFFF70A
H'3C
87
0
Write data
Figure 24.1 Writing to MSTCR
Rev.2.0, 07/03, page 853 of 960