SH7055S Datasheet, PDF (233/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 11.1 ATU-II Functions
Item
Channel 0
Channel 1
Channel 2
Channels 3–5
Counter
configu-
ration
Clock
sources
φ–φ/32
(φ–φ/32) × (1/2n)
(n = 0–5)
TCLKA, TCLKB,
AGCK, AGCKM
(φ–φ/32) × (1/2n)
(n = 0–5)
TCLKA, TCLKB,
AGCK, AGCKM
(φ–φ/32) × (1/2n)
(n = 0–5)
TCLKA, TCLKB,
AGCK, AGCKM
Counters TCNT0H, TCNT0L TCNT1A, TCNT1B TCNT2A, TCNT2B TCNT3–5
General —
registers
GR1A–H
GR2A–H
GR3A–D, GR4A–D,
GR5A–D
Dedicated ICR0AH, ICR0AL, OSBR1
OSBR2
—
input
ICR0BH, ICR0BL,
capture ICR0CH, ICR0CL,
ICR0DH, ICR0DL
Dedicated —
output
compare
OCR1
OCR2A–2H
—
PWM
—
—
—
Duty: GR3A–C,
output
GR4A–C, GR5A–C
Cycle: GR3D, GR4D,
GR5D
Input pins
TI0A–D
—
—
—
I/O pins
—
TIO1A–H
TIO2A–H
TIO3A–D, TIO4A–D,
TIO5A–D
Output pins
—
—
—
—
Counter clearing
—
—
—
O
function
Interrupt sources
6 sources
9 sources
9 sources
15 sources
Interval × 1,
input capture × 4,
overflow × 1
Dual input capture/ Dual input capture/ Dual input capture/
compare-match × 8, compare-match × 8, compare-match × 12,
overflow × 1
overflow × 1*
overflow × 3
(* Same vector)
Inter-channel and
inter-module
connection signals
A/D converter
Compare-match Compare-match Channel 9 compare-
activation by interval signal trigger output signal trigger output match signal input to
interrupt request, to channel 8
to channel 8
capture trigger
DMAC activation by one-shot pulse
one-shot pulse
(Channel 3 only)
input capture
output down-counter output down-counter
interrupt, channel 10 _{Channel 10 compare- Channel 10 compare-}
compare-match
match signal counter match signal counter
signal capture trigger _{clear input}
clear input
input
Rev.2.0, 07/03, page 195 of 960