SH7055S Datasheet, PDF (89/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 2.13 Arithmetic Operation Instructions (cont)
Instruction
Instruction Code
Operation
Execu-
tion
Cycles T Bit
SUB
Rm,Rn
0011nnnnmmmm1000 Rn – Rm → Rn
1
—
SUBC Rm,Rn
0011nnnnmmmm1010 Rn – Rm – T → Rn,
1
Borrow → T
Borrow
SUBV Rm,Rn
0011nnnnmmmm1011 Rn – Rm → Rn,
Underflow → T
1
Overflow
Note: * The normal minimum number of execution cycles. (The number in parentheses is the
number of cycles when there is contention with following instructions.)
Table 2.14 Logic Operation Instructions
Instruction
AND Rm,Rn
AND #imm,R0
AND.B #imm,@(R0,GBR)
NOT Rm,Rn
OR Rm,Rn
OR #imm,R0
OR.B #imm,@(R0,GBR)
TAS.B @Rn
TST Rm,Rn
TST #imm,R0
TST.B #imm,@(R0,GBR)
XOR Rm,Rn
XOR #imm,R0
XOR.B #imm,@(R0,GBR)
Instruction Code
0010nnnnmmmm1001
11001001iiiiiiii
11001101iiiiiiii
0110nnnnmmmm0111
0010nnnnmmmm1011
11001011iiiiiiii
11001111iiiiiiii
0100nnnn00011011
0010nnnnmmmm1000
11001000iiiiiiii
11001100iiiiiiii
0010nnnnmmmm1010
11001010iiiiiiii
11001110iiiiiiii
Operation
Execu-
tion
Cycles T Bit
Rn & Rm → Rn
1
—
R0 & imm → R0
1
—
(R0 + GBR) & imm → 3
—
(R0 + GBR)
~Rm → Rn
1
—
Rn | Rm → Rn
1
—
R0 | imm → R0
1
—
(R0 + GBR) | imm →
3
—
(R0 + GBR)
If (Rn) is 0, 1 → T; 1 → 4
MSB of (Rn)
Test
result
Rn & Rm; if the result is 1
0, 1 → T
Test
result
R0 & imm; if the result is 1
0, 1 → T
Test
result
(R0 + GBR) & imm; if the 3
result is 0, 1 → T
Test
result
Rn ^ Rm → Rn
1
—
R0 ^ imm → R0
1
—
(R0 + GBR) ^ imm → 3
—
(R0 + GBR)
Rev.2.0, 07/03, page 51 of 960