SH7055S Datasheet, PDF (934/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

26.3.9 HCAN Timing
Table 26.14 shows HCAN timing.
Table 26.14 HCAN Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 125°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing on-chip flash memory, T_a = –40°C to 85°C.
Item
Symbol Min
Max
Unit
Figures
Transmit data delay time
t
—
100
ns
Figure 26.18
HTxD
Transmit data setup time
t
100
—
ns
HRxS
Transmit data hold time
t_HRxH
100
—
ns
[Operating precautions]
The HCAN input signals are asynchronous, but judged to have been changed at CK clock rise
(two-clock intervals) shown in figure 26.18. The HCAN output signals are asynchronous, but they
change with a reference of CK clock rise (two-clock intervals) shown in figure 26.18.
V_OH
CK
HTxD0, HTxD1
(transmit data)
HRxD0, HRxD1
(receive data)
t_HTxD
V_OH
t_HRxS t_HRxH
Figure 26.18 HCAN Input/Output timing
Rev.2.0, 07/03, page 896 of 960