SH7055S Datasheet, PDF (43/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 1.1 SH7055SF Features (cont)
Item
Watchdog timer
(WDT)
(1 channel)
Compare-match
timer (CMT)
(2 channels)
Serial
communication
interface (SCI)
(5 channels)
Controller area
network (HCAN)
(2 channels)
A/D converter
High-
Performance
user debug
interface (H-UDI)
Features
• Can be switched between watchdog timer and interval timer function
• Internal reset, external signal, or interrupt generated by counter overflow
• Two kinds of internal reset
 Power-on reset
 Manual reset
• Selection of 4 counter input clocks
• A compare-match interrupt can be requested independently for each
channel
• Selection of asynchronous or synchronous mode
• Simultaneous transmission/reception (full-duplex) capability
• Serial data communication possible between multiple processors
(asynchronous mode)
• Clock inversion function
• LSB-/MSB-first selection function for transmission
• CAN version: Bosch 2.0B active compatible
• Buffer size (per channel): Transmit/receive × 15, receive-only × 1
• Receive message filtering capability
• Thirty-two channels
• Three sample-and-hold circuits
 Independent operation of 12 channels × 2 and 8 channels × 1
• Selection of two conversion modes
 Single conversion mode
 Scan mode
• Continuous scan mode
• Single-cycle scan mode
• Can be activated by external trigger or ATU-II compare-match
• 10-bit resolution
• Accuracy: ±2 LSB
• Five dedicated pins
• Bypass mode (test mode compliant with IEEE1149.1)
• H-UDI interrupt
Rev.2.0, 07/03, page 5 of 960