SH7055S Datasheet, PDF (140/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 7.3 Interrupt Exception Processing Vectors and Priorities (cont)
Interrupt Source
Interrupt Vector
Vector Table
Vector Address
No. Offset
Interrupt
Priority
(Initial
Value)
Priority
Corre- within IPR
sponding Setting Default
IPR (Bits) Range
Priority
ATU0
ATU01 ITV1/ 80
ITV2A/
ITV2B
H'00000140 to 0 to 15 (0) IPRC
H'00000143
(7–4)
High
ATU02 ICI0A 84
H'00000150 to 0 to 15 (0) IPRC
H'00000153
(3–0)
↑1
ICI0B 86
H'00000158 to
H'0000015B
↓2
ATU03 ICI0C 88
H'00000160 to 0 to 15 (0) IPRD
↑1
H'00000163
(15–12)
ICI0D 90
H'00000168 to
H'0000016B
↓2
ATU04 OVI0 92
H'00000170 to 0 to 15 (0) IPRD
H'00000173
(11–8)
ATU1 ATU11 IMI1A/C 96
MI1
H'00000180 to 0 to 15 (0) IPRD
H'00000183
(7–4)
↑1
IMI1B 97
H'00000184 to
2
H'00000187
IMI1C 98
H'00000188 to
3
H'0000018B
IMI1D 99
H'0000018C to
H'0000018F
↓4
ATU12 IMI1E 100 H'00000190 to 0 to 15 (0) IPRD
H'00000193
(3–0)
↑1
IMI1F 101 H'00000194 to
2
H'00000197
IMI1G 102 H'00000198 to
3
H'0000019B
IMI1H 103
H'0000019C to
H'0000019F
↓4
ATU13 OVI1A/ 104 H'000001A0 to 0 to 15 (0) IPRE
Low
OVI1B
H'000001A3
(15–12)
Rev.2.0, 07/03, page 102 of 960