SH7055S Datasheet, PDF (492/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

14.5 Usage Notes
Take care that the contentions described in sections 14.5.1 to 14.5.3 do not arise during CMT
operation.
14.5.1 Contention between CMCNT Write and Compare Match
If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the
CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure
14.6 shows the timing.
CMCNT write cycle
T1
T2
Pφ
Address
CMCNT
Internal
write signal
Compare
match signal
CMCNT
N
H'0000
Figure 14.6 CMCNT Write and Compare Match Contention
Rev.2.0, 07/03, page 454 of 960