SH7055S Datasheet, PDF (389/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Timer Interrupt Enable Register 10 (TIER10): TIER10 is a 16-bit readable/writable register
that controls enabling/disabling of channel 10 input capture and compare-match interrupt requests.
TIER10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software
standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
IREG CME10G CME10B ICE10A CME10A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W R/W R/W R/W R/W
• Bits 15 to 5—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 4—Interrupt Enable Edge G (IREG): Specifies TSR10 CMF10G interrupt request timing.
Bit 4: IREG
0
1
Description
Interrupt is requested when CMF10G becomes 1
(Initial value)
Interrupt is requested by next external input (TI10) (AGCK) after CMF10G
becomes 1
• Bit 3—Compare-Match Interrupt Enable 10G (CME10G): Enables or disables interrupt
requests by CMF10G in TSR10 when CMF10G is set to 1.
Bit 3: CME10G
0
1
Description
CMI10G interrupt requested by CMF10G is disabled
CMI10G interrupt requested by CMF10G is enabled
(Initial value)
• Bit 2—Compare-Match Interrupt Enable 10B (CME10B): Enables or disables interrupt
requests by CMF10B in TSR10 when CMF10B is set to 1.
Bit 2: CME10B
0
1
Description
CMI10B interrupt requested by CMF10B is disabled
CMI10B interrupt requested by CMF10B is enabled
(Initial value)
Rev.2.0, 07/03, page 351 of 960