SH7055S Datasheet, PDF (321/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

TIER1B: TIER1B controls enabling/disabling of channel 1 compare-match and overflow
interrupt requests.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
— OVE1B
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
— CME1
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Interrupt Enable 1B (OVE1B): Enables or disables interrupt requests by
OVF1B in TSR1B when OVF1B is set to 1.
Bit 8: OVE1B
0
1
Description
OVI1B interrupt requested by OVF1B is disabled
OVI1B interrupt requested by OVF1B is enabled
(Initial value)
• Bits 7 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 0—Compare-Match Interrupt Enable 1 (CME1): Enables or disables interrupt requests by
CMF1 in TSR1B when CMF1 is set to 1.
Bit 0: CME1
0
1
Description
CMI1 interrupt requested by CMF1 is disabled
CMI1 interrupt requested by CMF1 is enabled
(Initial value)
Rev.2.0, 07/03, page 283 of 960