SH7055S Datasheet, PDF (32/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

16.3.6 HCAN Halt Mode ................................................................................................ 575
16.3.7 Interrupt Interface ................................................................................................ 575
16.3.8 DMAC Interface .................................................................................................. 576
16.4 CAN Bus Interface............................................................................................................ 578
16.5 Usage Notes ...................................................................................................................... 579
Section 17 A/D Converter .................................................................................583
17.1 Overview........................................................................................................................... 583
17.1.1 Features................................................................................................................ 583
17.1.2 Block Diagram ..................................................................................................... 584
17.1.3 Pin Configuration................................................................................................. 586
17.1.4 Register Configuration......................................................................................... 589
17.2 Register Descriptions ........................................................................................................ 591
17.2.1 A/D Data Registers 0 to 31 (ADDR0 to ADDR31) ............................................. 591
17.2.2 A/D Control/Status Registers 0 and 1 (ADCSR0, ADCSR1) .............................. 592
17.2.3 A/D Control Registers 0 to 2 (ADCR0 to ADCR2)............................................. 597
17.2.4 A/D Control/Status Register 2 (ADCSR2)........................................................... 599
17.2.5 A/D Trigger Registers 0 to 2 (ADTRGR0 to ADTRGR2) .................................. 602
17.3 CPU Interface.................................................................................................................... 603
17.4 Operation .......................................................................................................................... 604
17.4.1 Single Mode......................................................................................................... 604
17.4.2 Scan Mode ........................................................................................................... 606
17.4.3 Analog Input Sampling and A/D Conversion Time............................................. 610
17.4.4 External Triggering of A/D Conversion .............................................................. 612
17.4.5 A/D Converter Activation by ATU-II.................................................................. 613
17.4.6 ADEND Output Pin ............................................................................................. 613
17.5 Interrupt Sources and DMA Transfer Requests ................................................................ 614
17.6 Usage Notes ...................................................................................................................... 614
17.6.1 A/D conversion accuracy definitions................................................................... 616
Section 18 High-Performance User Debug Interface (H-UDI) ........................617
18.1 Overview........................................................................................................................... 617
18.1.1 Features................................................................................................................ 617
18.1.2 Block Diagram ..................................................................................................... 618
18.1.3 Pin Configuration................................................................................................. 619
18.1.4 Register Configuration......................................................................................... 619
18.2 External Signals ................................................................................................................ 620
18.2.1 Test Clock (TCK) ................................................................................................ 620
18.2.2 Test Mode Select (TMS)...................................................................................... 620
18.2.3 Test Data Input (TDI) .......................................................................................... 620
18.2.4 Test Data Output (TDO) ...................................................................................... 620
18.2.5 Test Reset (TRST) ............................................................................................... 620
18.3 Register Descriptions ........................................................................................................ 621
Rev.2.0, 07/03, page xxxii of xxxviii