SH7055S Datasheet, PDF (303/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 9—Overflow Flag 4 (OVF4): Status flag that indicates TCNT4 overflow.
Bit 9: OVF4
0
1
Description
[Clearing condition]
When OVF4 is read while set to 1, then 0 is written to OVF4
[Setting condition]
When the TCNT4 value overflows (from H'FFFF to H'0000)
(Initial value)
• Bit 8—Input Capture/Compare-Match Flag 4D (IMF4D): Status flag that indicates GR4D
input capture or compare-match.
Bit 8: IMF4D
0
1
Description
[Clearing condition]
(Initial value)
When IMF4D is read while set to 1, then 0 is written to IMF4D
[Setting conditions]
• When the TCNT4 value is transferred to GR4D by an input capture signal
while GR4D is functioning as an input capture register
• When TCNT4 = GR4D while GR4D is functioning as an output compare
register
• When TCNT4 = GR4D while GR4D is functioning as a PWM mode
synchronous register
• Bit 7—Input Capture/Compare-Match Flag 4C (IMF4C): Status flag that indicates GR4C input
capture or compare-match. The flag is not set in PWM mode.
Bit 7: IMF4C
0
1
Description
[Clearing condition]
(Initial value)
When IMF4C is read while set to 1, then 0 is written to IMF4C
[Setting conditions]
• When the TCNT4 value is transferred to GR4C by an input capture signal
while GR4C is functioning as an input capture register
• When TCNT4 = GR4C while GR4C is functioning as an output compare
register
Rev.2.0, 07/03, page 265 of 960