SH7055S Datasheet, PDF (171/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

8.5.5 User Break Trigger Output
Information on internal bus condition matches monitored by the UBC is output as UBCTRG. The
trigger width can be set with clock select bits 1 and 0 (CKS1, CKS0) in the user break control
register (UBCR).
If a condition matches occurs again during trigger output, the UBCTRG pin continues to output a
low level, and outputs a pulse of the length set in bits CKS1 and CKS0 from the cycle in which the
last condition match occurs.
The trigger output conditions differ from those in the case of a user break interrupt when a CPU
instruction fetch condition is satisfied. When a condition occurs in an overrun fetch instruction as
described in section 8.5.2, Instruction Fetch at Branches, a user break interrupt is not requested but
a trigger is output from the UBCTRG pin.
In other CPU data accesses and DMAC bus cycles, pulse output is performed under conditions
similar to user break interrupt conditions.
Setting the user break interrupt disable (UBID) bit to 1 in UBCR enables trigger output to be
monitored externally without requesting a user break interrupt.
8.5.6 Module Standby
After a power-on reset the UBC is in the module standby state, in which the clock supply is halted.
When using the UBC, the module standby state must be cleared before making UBC register
settings. Module standby is controlled by the module standby control register (MSTCR). See
section 24.2.3, Module Standby Control Register (MSTCR), for further details.
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