SH7055S Datasheet, PDF (420/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

OSF Setting Timing in Underflow: When a down-counter (DCNT) counts down from H'0001 to
H'0000 on DCNT input clock input, the OSF bit is set to 1 in the timer status register (TSR) when
the next DCNT input clock pulse is input (when underflow occurs). However, when DCNT is
H'0000, it remains unchanged at H'0000 no matter how many DCNT input clock pulses are input.
When DCNT is cleared by means of the one-shot pulse function, the OSF bit is cleared when the
next DCNT input clock is input.
The timing in this case is shown in figure 11.40.
CK
DCNT input clock
DCNT H'0001
H'0000
H'0000
Underflow signal
Interrupt status flag
OSF
Interrupt request signal
OSI
Figure 11.40 OSF Setting Timing in Underflow
Rev.2.0, 07/03, page 382 of 960