SH7055S Datasheet, PDF (135/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

7.1.3 Pin Configuration
Table 7.1 shows the INTC pin configuration.
Table 7.1 Pin Configuration
Name
Non-maskable interrupt input pin
Abbreviation I/O
NMI
I
Interrupt request input pins
IRQ0–IRQ7 I
Interrupt request output pin
IRQOUT
O
Function
Input of non-maskable interrupt
request signal
Input of maskable interrupt request
signals
Output of notification signal when an
interrupt has occurred
7.1.4 Register Configuration
The INTC has the 14 registers shown in table 7.2. These registers set the priority of the interrupts
and control external interrupt input signal detection.
Table 7.2 Register Configuration
Name
Abbr. R/W Initial Value Address
Access Sizes
Interrupt priority register A IPRA R/W H'0000
H'FFFF ED00 8, 16, 32
Interrupt priority register B IPRB R/W H'0000
H'FFFF ED02 8, 16, 32
Interrupt priority register C IPRC R/W H'0000
H'FFFF ED04 8, 16, 32
Interrupt priority register D IPRD R/W H'0000
H'FFFF ED06 8, 16, 32
Interrupt priority register E IPRE R/W H'0000
H'FFFF ED08 8, 16, 32
Interrupt priority register F IPRF R/W H'0000
H'FFFF ED0A 8, 16, 32
Interrupt priority register G IPRG R/W H'0000
H'FFFF ED0C 8, 16, 32
Interrupt priority register H IPRH R/W H'0000
H'FFFF ED0E 8, 16, 32
Interrupt priority register I IPRI R/W H'0000
H'FFFF ED10 8, 16, 32
Interrupt priority register J IPRJ R/W H'0000
H'FFFF ED12 8, 16, 32
Interrupt priority register K IPRK R/W H'0000
H'FFFF ED14 8, 16, 32
Interrupt priority register L
Interrupt control register
IRQ status register
IPRL
ICR
ISR
R/W
R/W
R(W)*²
H'0000
*¹
H'0000
H'FFFF ED16
H'FFFF ED18
H'FFFF ED1A
8, 16, 32
8, 16, 32
8, 16, 32
Notes: Three access cycles are required for byte access and word access, and six cycles for
longword access.
*1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000.
*2. Only 0 can be written, in order to clear flags.
Rev.2.0, 07/03, page 97 of 960