SH7055S Datasheet, PDF (158/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

8.1.2 Block Diagram
Figure 8.1 shows a block diagram of the UBC.
Module bus
Bus
interface
UBCR
UBBR
UBAMRH UBARH
UBAMRL UBARL
Break condition
comparator
User break
interrupt
generating
circuit
Trigger output
generating
circuit
Interrupt request
Interrupt controller
pin output
UBARH, UBARL: User break address registers H, L
UBAMRH, UBAMRL: User break address mask registers H, L
UBBR: User break bus cycle register
UBCR: User break control register
Figure 8.1 User Break Controller Block Diagram
Rev.2.0, 07/03, page 120 of 960