SH7055S Datasheet, PDF (469/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 13 Watchdog Timer (WDT)
13.1 Overview
The watchdog timer (WDT) is a 1-channel timer for monitoring system operations. If a system
encounters a problem (crashes, for example) and the timer counter overflows without being
rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT
can simultaneously generate an internal reset signal for the entire chip.
When the watchdog function is not needed, the WDT can be used as an interval timer. In the
interval timer operation, an interval timer interrupt is generated at each counter overflow.
13.1.1 Features
The WDT has the following features:
• Works in watchdog timer mode or interval timer mode
• Outputs WDTOVF in watchdog timer mode
When the counter overflows in watchdog timer mode, overflow signal WDTOVF is output
externally. It is possible to select whether to reset the chip internally when this happens. Either
the power-on reset or manual reset signal can be selected as the internal reset signal.
• Generates interrupts in interval timer mode
When the counter overflows, it generates an interval timer interrupt.
• Works with eight counter input clocks
Rev.2.0, 07/03, page 431 of 960