SH7055S Datasheet, PDF (34/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

20.3.11 Port E Control Register (PECR) .......................................................................... 666
20.3.12 Port F IO Register (PFIOR) ................................................................................. 671
20.3.13 Port F Control Registers H and L (PFCRH, PFCRL) .......................................... 672
20.3.14 Port G IO Register (PGIOR) ................................................................................ 677
20.3.15 Port G Control Register (PGCR).......................................................................... 678
20.3.16 Port H IO Register (PHIOR) ................................................................................ 679
20.3.17 Port H Control Register (PHCR).......................................................................... 680
20.3.18 Port J IO Register (PJIOR)................................................................................... 686
20.3.19 Port J Control Registers H and L (PJCRH, PJCRL) ............................................ 687
20.3.20 Port K IO Register (PKIOR) ................................................................................ 691
20.3.21 Port K Control Registers H and L (PKCRH, PKCRL) ........................................ 691
20.3.22 Port K Invert Register (PKIR) ............................................................................. 696
20.3.23 Port L IO Register (PLIOR)................................................................................. 697
20.3.24 Port L Control Registers H and L (PLCRH, PLCRL).......................................... 698
20.3.25 Port L Invert Register (PLIR) .............................................................................. 703
Section 21 I/O Ports (I/O)..................................................................................705
21.1 Overview........................................................................................................................... 705
21.2 Port A................................................................................................................................ 705
21.2.1 Register Configuration......................................................................................... 706
21.2.2 Port A Data Register (PADR) .............................................................................. 706
21.2.3 Port A Port Register (PAPR) ............................................................................... 707
21.3 Port B ................................................................................................................................ 708
21.3.1 Register Configuration......................................................................................... 708
21.3.2 Port B Data Register (PBDR) .............................................................................. 709
21.3.3 Port B Port Register (PBPR) ................................................................................ 710
21.4 Port C ................................................................................................................................ 710
21.4.1 Register Configuration......................................................................................... 710
21.4.2 Port C Data Register (PCDR) .............................................................................. 711
21.5 Port D................................................................................................................................ 712
21.5.1 Register Configuration......................................................................................... 712
21.5.2 Port D Data Register (PDDR) .............................................................................. 713
21.5.3 Port D Port Register (PDPR) ............................................................................... 714
21.6 Port E ................................................................................................................................ 715
21.6.1 Register Configuration......................................................................................... 715
21.6.2 Port E Data Register (PEDR)............................................................................... 716
21.7 Port F................................................................................................................................. 718
21.7.1 Register Configuration......................................................................................... 718
21.7.2 Port F Data Register (PFDR) ............................................................................... 719
21.8 Port G................................................................................................................................ 720
21.8.1 Register Configuration......................................................................................... 721
21.8.2 Port G Data Register (PGDR) .............................................................................. 721
21.9 Port H................................................................................................................................ 723
Rev.2.0, 07/03, page xxxiv of xxxviii