SH7055S Datasheet, PDF (451/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Input Capture Operation when Free-Running Counter is Halted: In channels 0 to 5, channel
10, or channel 11, if input capture setting is performed and a trigger signal is input from the input
pin, the TCNT value will be transferred to the corresponding general register (GR) or input
capture register (ICR) irrespective of whether the free-running counter (TCNT) is running or
halted, and the IMF or ICF bit will be set in the timer status register (TSR).
The timing in this case is shown in figure 11.71.
Pø
Timer status register
TSR
Internal input capture
signal
TCNT
N
GR (ICR)
N
Interrupt status flag
IMF (ICF)
Figure 11.71 Input Capture Operation before Free-Running Counter is Started
Rev.2.0, 07/03, page 413 of 960