SH7055S Datasheet, PDF (343/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.2.8 Trigger Mode Register (TRGMDR)
The trigger mode register (TRGMDR) is an 8-bit register. The ATU-II has one TRGMDR register.
Bit: 7
6
5
4
3
2
1
0
TRGMD —
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R
R
TRGMDR is an 8-bit readable/writable register that selects whether a channel 1 compare-match is
used as a channel 8 one-shot pulse start trigger or as a one-shot pulse terminate trigger when
channel 1 and channel 8 are used in combination.
TRGMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
• Bit 7—Trigger Mode Selection Register (TRGMD): Selects the channel 8 one-shot pulse start
trigger/one-shot pulse terminate trigger setting.
Bit 7: TRGMD
0
1
Description
One-shot pulse start trigger (TCNT1B = OCR1)
One-shot pulse terminate trigger (TCNT1A = GR1A–GR1H)
One-shot pulse start trigger (TCNT1A = GR1A–GR1H)
One-shot pulse terminate trigger (TCNT1B = OCR1)
(Initial value)
• Bits 6 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
11.2.9 Timer Mode Register (TMDR)
The timer mode register (TMDR) is an 8-bit register. The ATU-II has one TDR register.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
— T5PWM T4PWM T3PWM
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
TMDR is an 8-bit readable/writable register that specifies whether channels 3 to 5 are used in
input capture/output compare mode or PWM mode.
TMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Rev.2.0, 07/03, page 305 of 960