SH7055S Datasheet, PDF (786/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 22.5 Register/Parameter and Target Mode
Initiali-
Download zation
Program-
RAM
ming
Erasure Read Emulation
Programming/ FCCS O
—
—
—
—
—
erasing
FPCS
O
—
—
—
—
—
interface
registers
PECS O
FKEY
O
FMATS —
—
—
—
—
—
—
O
O
—
—
—
O*¹
O*¹
O*²
—
FTDAR O
—
—
—
—
—
Programming/ DPFR O
—
—
—
—
—
erasing
FPFR
O
O
O
O
—
—
interface
parameters
FPEFEQ —
FUBRA —
O
—
—
—
—
O
—
—
—
—
FMPAR —
—
O
—
—
—
FMPDR —
—
O
—
—
—
FEBS
—
—
—
O
—
—
RAM
emulation
RAMER —
—
—
—
—
O
Notes: *1 The setting is required when programming or erasing user MAT in user boot mode.
*2 The setting may be required according to the combination of initiation mode and read
target MAT.
22.4.2 Programming/Erasing Interface Registers
The programming/erasing interface registers are as described below. They are all 8-bit registers
that can be accessed in bytes. Except for the FLER bit in FCCS and FMATS, these registers are
initialized at a power-on reset, in hardware standby mode, or in software standby mode. The
FLER bit or FMATS is not initialized in software standby mode.
(1) Flash Code Control and Status Register (FCCS)
FCCS is configured by bits which request the monitor of the FWE pin state and error
occurrence during programming or erasing flash memory and the download of the on-chip
program.
Bit
:
7
6
5
4
3
2
1
0
FWE
—
—
FLER
—
—
—
SCO
Initial value : 1/0
0
0
0
0
0
0
0
R/W
:
R
R
R
R
R
R
R
(R)/W
Rev.2.0, 07/03, page 748 of 960