SH7055S Datasheet, PDF (163/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bits 5 and 4—Instruction Fetch/Data Access Select (ID1, ID0): These bits select whether to
break on instruction fetch and/or data access cycles.
Bit 5: ID1
0
1
Bit 4: ID0
0
1
0
1
Description
No user break interrupt occurs
(Initial value)
Break on instruction fetch cycles
Break on data access cycles
Break on both instruction fetch and data access cycles
• Bits 3 and 2—Read/Write Select (RW1, RW0): These bits select whether to break on read
and/or write cycles.
Bit 3: RW1
0
1
Bit 2: RW0
0
1
0
1
Description
No user break interrupt occurs
Break on read cycles
Break on write cycles
Break on both read and write cycles
(Initial value)
• Bits 1 and 0—Operand Size Select (SZ1, SZ0): These bits select operand size as a break
condition.
Bit 1: SZ1
Bit 0: SZ0
Description
0
0
Operand size is not a break condition
(Initial value)
1
Break on byte access
1
0
Break on word access
1
Break on longword access
Note:
When breaking on an instruction fetch, clear the SZ0 bit to 0. All instructions are considered
to be word-size accesses (even when there are instructions in on-chip memory and two
instruction fetches are performed simultaneously in one bus cycle).
Operand size is word for instructions or determined by the operand size specified for the
CPU/DMAC data access. It is not determined by the bus width of the space being
accessed.
Rev.2.0, 07/03, page 125 of 960