SH7055S Datasheet, PDF (444/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.7 Usage Notes
Note that the kinds of operation and contention described below occur during ATU operation.
Contention between TCNT Write and Clearing by Compare-Match: With channel 3 to 7 free-
running counters (TCNT3 to TCNT5, TCNT6A to TCNT6D, TCNT7A to TCNT7D), if a
compare-match occurs in the T2 state of a CPU write cycle when counter clearing by compare-
match has been set, or when PWM mode is used, the write to TCNT has priority and TCNT
clearing is not performed.
The compare-match remains valid, and writing of 1 to the interrupt status flag and waveform
output to an external destination are performed in the same way as for a normal compare-match.
The timing in this case is shown in figure 11.64.
Pø
Address
T1
T2
TCNT address
Internal write signal
Compare-match signal
Counter clear signal
TCNT
CPU write value
Interrupt status flag
External output signal
(1 output)
Figure 11.64 Contention between TCNT Write and Clear
Rev.2.0, 07/03, page 406 of 960