SH7055S Datasheet, PDF (629/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

17.2 Register Descriptions
17.2.1 A/D Data Registers 0 to 31 (ADDR0 to ADDR31)
A/D data registers 0 to 31 (ADDR0 to ADDR31) are 16-bit read-only registers that store the
results of A/D conversion. There are 31 registers, corresponding to analog inputs 0 to 31 (AN0 to
AN31).
The ADDR registers are initialized to H'0000 by a power-on reset, and in hardware standby mode
and software standby mode.
Bit: 7
6
5
4
3
2
1
0
ADDRnH
(upper byte)
AD9
AD8
AD7
AD6
AD5
ADR
AD3
AD2
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
ADDRnL
(lower byte)
AD1
AD0
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
(n = 0 to 31)
The A/D converter converts analog input to a 10-bit digital value. The upper 8 bits of this data are
stored in the upper byte of the ADDR corresponding to the selected channel, and the lower 2 bits
in the lower byte of that ADDR. Only the most significant 2 bits of the ADDR lower byte data are
valid.
Table 17.3 shows correspondence between the analog input channels and A/D data registers.
Rev.2.0, 07/03, page 591 of 960