SH7055S Datasheet, PDF (991/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table A.2 Register States in Reset and Power-Down States (cont)
Type
Advanced timer
unit-II (ATU-II)
Advanced pulse
controller (APC)
Watchdog timer
(WDT)
Serial
communication
interface (SCI)
A/D converter
Name
TIER0, TIER1A, 1B
TIER2A, 2B, TIER3
TIER6-11
TIOR0, TIOR1A-D
TIOR2A-D, TIOR3A
3B, TIOR4A, 4B
TIOR5A, 5B
TIOR10,11
TMDR
TNCT10E
TRGMDR
TSR0, TSR1A, 1B
TSR2A, 2B, TSR3
TSR6-11
TSTR1-3
POPCR
TCNT
TCSR
RSTCSR
SMR0 to SMR4
BRR0 to BRR4
SCR0 to SCR4
TDR0 to TDR4
SSR0 to SSR4
RDR0 to RDR4
SDCR0 to SDCR4
ADDR0 (H/L) to
ADDR31 (H/L)
ADSCR0, ADCSR1
ADCSR2
ADCR0, ADCR1
ADCR2
Reset State Power-Down State
Hardware Software
Power-On Standby Standby
Initialized Initialized Initialized
Initialized
Initialized
Initialized Held
Initialized Initialized
Initialized Initialized Held
Intialized
Initialized
Initialized
Held
Initialized
Sleep
Held
Held
Held
Held
Held
Rev.2.0, 07/03, page 953 of 960