SH7055S Datasheet, PDF (674/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

If another branch occurs during branch destination address output, the later branch has priority for
output. In this case, AUDSYNC is negated and the AUDATA pins output the address after
outputting 10xx again (figure 19.3 shows an example of the output when consecutive branches
occur). Note that the compared address is the previous fully output address, and not an interrupted
address (since the upper address of an interrupted address will be unknown).
The interval from the start of execution at the branch destination address in the PC until the
AUDATA pins output 10xx is 1.5 or 2 AUDCK cycles.
Start of execution at branch destination address in PC
AUDCK
AUDATA [3:0] 0011 0011 1011 A3–A0 A7–A4 A11–A8 A15–A12 A19–A16 A23–A20 A27–A24 A31–A28 0011
Figure 19.2 Example of Data Output (32-Bit Output)
Start of execution at branch destination address in PC (1)
Start of execution at branch destination address in PC (2)
AUDCK
AUDATA [3:0] 0011 0011 1011 A3–A0 A7–A4 1010 A3–A0 A7–A4 A11–A8 A15–A12 0011 0011
Figure 19.3 Example of Output in Case of Successive Branches
Rev.2.0, 07/03, page 636 of 960