SH7055S Datasheet, PDF (796/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

(2.2) Flash user branch address setting parameter (FUBRA: general register R5 of CPU)
This parameter sets the user branch destination address. The user program which has been set
can be executed in specified processing units when programming and erasing.
Bit :
31
30
29
28
27
26
25
24
UA31 UA30 UA29 UA28 UA27 UA26 UA25 UA24
Bit :
23
22
21
20
19
18
17
16
UA23 UA22 UA21 UA20 UA19 UA18 UA17 UA16
Bit :
15
14
13
12
11
10
9
8
UA15 UA14 UA13 UA12 UA11 UA10 UA9 UA8
Bit :
7
6
5
4
3
2
1
0
UA7
UA6
UA5
UA4 UA3
UA2
UA1
UA0
Bits 31 to 0—User Branch Destination Address (UA31 to UA0): When the user branch is not
required, address 0 (H'00000000) must be set.
The user branch destination must be an area other than the flash memory, an area other than the
RAM area in which on-chip program has been transferred, or the external bus space.
Note that the CPU must not branch to an area without the execution code and get out of control.
The on-chip program download area and stack area must not be overwritten. If CPU runaway
occurs or the download area or stack area is overwritten, the value of flash memory cannot be
guaranteed.
The download of the on-chip program, initialization, initiation of the programming/erasing
program must not be executed in the processing of the user branch destination. Programming or
erasing cannot be guaranteed when returning from the user branch destination. The program data
which has already been prepared must not be programmed.
The general registers R8 to R15 are stored. The general registers R0 to R7 can be used without
being stored.
Moreover, the programming/erasing interface registers must not be written to or RAM emulation
mode must not be entered in the processing of the user branch destination.
After the processing of the user branch has ended, the programming/erasing program must be
returned to by using the RTS instruction.
For the execution intervals of the user branch processing, see note 2 (User branch processing
intervals) in section 22.8.3, Other Notes.
Rev.2.0, 07/03, page 758 of 960