SH7055S Datasheet, PDF (754/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

21.6.2 Port E Data Register (PEDR)
Bit: 15
14
13
12
11
10
9
8
PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8
DR
DR
DR
DR
DR
DR
DR
DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
DR
DR
DR
DR
DR
DR
DR
DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port E data register (PEDR) is a 16-bit readable/writable register that stores port E data. Bits
PE15DR to PE0DR correspond to pins PE15/A15 to PE0/A0.
When a pin functions as a general output, if a value is written to PEDR, that value is output
directly from the pin, and if PEDR is read, the register value is returned directly regardless of the
pin state. When the POD pin is driven low, general outputs go to the high-impedance state
regardless of the PEDR value. When the POD pin is driven high, the written value is output from
the pin.
When a pin functions as a general input, if PEDR is read the pin state, not the register value, is
returned directly. If a value is written to PEDR, although that value is written into PEDR it does
not affect the pin state. Table 21.10 summarizes port E data register read/write operations.
PEDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
Rev.2.0, 07/03, page 716 of 960