SH7055S Datasheet, PDF (301/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Timer Status Register 3 (TSR3)
TSR3 indicates the status of channel 3 to 5 input capture, compare-match, and overflow.
Bit: 15
14
13
12
11
10
9
8
—
OVF5 IMF5D IMF5C IMF5B IMF5A OVF4 IMF4D
Initial value: 0
0
0
0
0
0
0
0
R/W: R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Bit:
Initial value:
R/W:
7
IMF4C
0
R/(W)*
6
IMF4B
0
R/(W)*
5
IMF4A
0
R/(W)*
4
OVF3
0
R/(W)*
3
IMF3D
0
R/(W)*
2
IMF3C
0
R/(W)*
1
IMF3B
0
R/(W)*
0
IMF3A
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
• Bit 15—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 14—Overflow Flag 5 (OVF5): Status flag that indicates TCNT5 overflow.
Bit 14: OVF5
0
1
Description
[Clearing condition]
When OVF5 is read while set to 1, then 0 is written to OVF5
[Setting condition]
When the TCNT5 value overflows (from H'FFFF to H'0000)
(Initial value)
• Bit 13—Input Capture/Compare-Match Flag 5D (IMF5D): Status flag that indicates GR5D
input capture or compare-match.
Bit 13: IMF5D
0
1
Description
[Clearing condition]
(Initial value)
When IMF5D is read while set to 1, then 0 is written to IMF5D
[Setting conditions]
• When the TCNT5 value is transferred to GR5D by an input capture signal
while GR5D is functioning as an input capture register
• When TCNT5 = GR5D while GR5D is functioning as an output compare
register
• When TCNT5 = GR5D while GR5D is functioning as a cycle register in
PWM mode
Rev.2.0, 07/03, page 263 of 960