MC9S12XD256MAL Datasheet, PDF (999/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Table 24-17. PTT Field Descriptions
Field
7–0
PTT[7:0]
Description
Port T — Port T bits 7–0 are associated with ECT channels IOC7–IOC0 (refer to ECT section). When not used
with the ECT, these pins can be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port
register, otherwise the buffered pin input state is read.
24.0.5.14 Port T Input Register (PTIT)
7
R PTIT7
6
PTIT6
5
PTIT5
4
PTIT4
3
PTIT3
2
PTIT2
1
PTIT1
0
PTIT0
W
Reset¹
—
—
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 24-16. Port T Input Register (PTIT)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
Read: Anytime.
Write: Never, writes to this register have no effect.
Table 24-18. PTIT Field Descriptions
Field
Description
7–0
Port T Input — This register always reads back the buffered state of the associated pins. This can also be used
PTIT[7:0] to detect overload or short circuit conditions on output pins.
24.0.5.15 Port T Data Direction Register (DDRT)
R
W
Reset
7
DDRT7
0
6
DDRT6
5
DDRT5
4
DDRT4
3
DDRT3
2
DDRT2
0
0
0
0
0
Figure 24-17. Port T Data Direction Register (DDRT)
1
DDRT1
0
0
DDRT0
0
Read: Anytime.
Write: Anytime.
This register configures each port T pin as either input or output.
The ECT forces the I/O state to be an output for each timer port associated with an enabled output
compare. In this case the data direction bits will not change.