MC9S12XD256MAL Datasheet, PDF (908/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
Table 23-1. Pin Functions and Priorities (Sheet 7 of 7)
Port
Pin Name
Pin Function
and Priority
I/O
Description
TXCAN4
O MSCAN4 transmit pin
SCL0
O Inter Integrated Circuit 0 serial clock line
PJ7
TXCAN0
O MSCAN0 transmit pin
GPIO/KWJ7
RXCAN4
I/O General-purpose I/O with interrupt
I MSCAN4 receive pin
SDA0
I/O Inter Integrated Circuit 0 serial data line
PJ6
RXCAN0
I MSCAN0 receive pin
GPIO/KWJ6 I/O General-purpose I/O with interrupt
CS2
O Chip select 2
PJ5
J
GPIO/KWJ7 I/O General-purpose I/O with interrupt
CS0
O Chip select 0
PJ4
GPIO/KWJ6 I/O General-purpose I/O with interrupt
CS1
O Chip select 1
PJ2
GPIO/KWJ2 I/O General-purpose I/O with interrupt
TXD2
O Serial Communication Interface 2 transmit pin
PJ1
GPIO/KWJ1 I/O General-purpose I/O with interrupt
RXD2
I Serial Communication Interface 2 receive pin
PJ0
CS3
O Chip select 3
GPIO/KWJ0 I/O General-purpose I/O with interrupt
AD0 PAD[07:00]
GPIO
AN[7:0]
I/O General-purpose I/O
I ATD0 analog inputs
AD1 PAD[23:08]
GPIO
AN[15:0]
I/O General-purpose I/O
I ATD1 analog inputs
1. Function active when RESET asserted.
2. Only available in emulation modes or in Special Test Mode with IVIS on.
3. Refer also to Table 23-70 and S12X_EBI section.
Memory Map and Register Definition
This section provides a detailed description of all PIMregisters.
23.0.4 Module Memory Map
Table 23-2 shows the register map of the port integration module.
Pin Function
after Reset
GPIO
GPIO
GPIO
MC9S12XDP512 Data Sheet, Rev. 2.21
910
Freescale Semiconductor