MC9S12XD256MAL Datasheet, PDF(879/1348 Page) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

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MC9S12XD256MAL Datasheet, PDF (879/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

22.4 Functional Description

Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an

output from the external bus interface module or a peripheral module or an input to the external bus

interface module or a peripheral module.

A set of configuration registers is common to all ports with exceptions in the expanded bus interface and

ATD ports (Table 22-67). All registers can be written at any time; however a specific configuration might

not become active.

Example: Selecting a pull-up device

This device does not become active while the port is used as a push-pull output.

Table 22-67. Register Availability per Port1

Port

Data

Data

Direction

Input

Reduced

Drive

Pull

Enable

A

yes

yes

â

yes

yes

B

yes

yes

â

C

yes

yes

â

D

yes

yes

â

E

yes

yes

â

K

yes

yes

â

T

yes

yes

yes

yes

yes

S

yes

yes

yes

yes

yes

M

yes

yes

yes

yes

yes

P

yes

yes

yes

yes

yes

H

yes

yes

yes

yes

yes

J

yes

yes

yes

yes

yes

AD0

yes

yes

â

yes

yes

AD1

yes

yes

â

yes

yes

1 Each cell represents one register with individual conï¬guration bits

Polarity

Select

â

â

â

â

â

â

â

yes

yes

yes

yes

yes

â

â

Wired-OR

Mode

â

â

â

â

â

â

â

yes

yes

â

â

â

â

â

Interrupt

Enable

â

â

â

â

â

â

â

â

â

yes

yes

yes

â

â

Interrupt

Flag

â

â

â

â

â

â

â

â

â

yes

yes

yes

â

â

22.4.1 Registers

22.4.1.1 Data Register

This register holds the value driven out to the pin if the pin is used as a general purpose I/O.

Writing to this register has only an effect on the pin if the pin is used as general purpose output. When

reading this address, the buffered state of the pin is returned if the associated data direction register bit is

set to â0â.

If the data direction register bits are set to logic level â1â, the contents of the data register is returned. This

is independent of any other configuration (Figure 22-76).

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

881

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