MC9S12XD256MAL Datasheet, PDF (1266/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Appendix A Electrical Characteristics
If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and
SCME = 1), the system will resume operation in self-clock mode after t_fws.
A.5.1.5 Pseudo Stop and Wait Recovery
The recovery from pseudo stop and wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After t_wrs the CPU starts
fetching the interrupt vector.
A.5.2 Oscillator
The device features an internal low-power loop controlled Pierce oscillator and a full swing Pierce
oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce
oscillator/external clock depends on the XCLKS signal which is sampled during reset. Before asserting the
oscillator to the internal system clocks the quality of the oscillation is checked for each start from either
power-on, STOP or oscillator fail. t_CQOUT specifies the maximum time before switching to the internal self
clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines
the minimum oscillator start-up time t_UPOSC. The device also features a clock monitor. A clock monitor
failure is asserted if the frequency of the incoming clock signal is below the assert frequency f_CMFA.
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor