MC9S12XD256MAL Datasheet, PDF (628/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 17 Memory Mapping Control (S12XMMCV2)
Table 17-13. PPAGE Field Descriptions
Field
7–0
PIX[7:0]
Description
Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM
array pages is to be accessed in the Program Page Window.
The fixed 16K page from $4000–$7FFF (when ROMHM = 0) is the page number $FD.
The reset value of $FE ensures that there is linear Flash space available between addresses $4000 and
$FFFF out of reset.
The fixed 16K page from $C000-$FFFF is the page number $FF.
17.3.2.9 RAM Write Protection Control Register (RAMWPC)
Address: 0x011C
R
W
Reset
7
RWPE
0
6
5
4
3
2
1
0
0
0
0
0
AVIE
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 17-17. RAM Write Protection Control Register (RAMWPC)
0
AVIF
0
Read: Anytime
Write: Anytime
Table 17-14. RAMWPC Field Descriptions
Field
7
RWPE
1
AVIE
0
AVIF
Description
RAM Write Protection Enable — This bit enables the RAM write protection mechanism. When the RWPE bit
is cleared, there is no write protection and any memory location is writable by the CPU module and the XGATE
module. When the RWPE bit is set the write protection mechanism is enabled and write access of the CPU or
to the XGATE RAM region. Write access performed by the XGATE module to outside of the XGATE RAM region
or the shared region is suppressed as well in this case.
0 RAM write protection check is disabled, region boundary registers can be written.
1 RAM write protection check is enabled, region boundary registers cannot be written.
CPU Access Violation Interrupt Enable — This bit enables the Access Violation Interrupt. If AVIE is set and
AVIF is set, an interrupt is generated.
0 CPU Access Violation Interrupt Disabled.
1 CPU Access Violation Interrupt Enabled.
CPU Access Violation Interrupt Flag — When set, this bit indicates that the CPU has tried to write a memory
location inside the XGATE RAM region. This flag can be reset by writing’1’ to the AVIF bit location.
0 No access violation by the CPU was detected.
1 Access violation by the CPU was detected.
MC9S12XDP512 Data Sheet, Rev. 2.21
628
Freescale Semiconductor