MC9S12XD256MAL Datasheet, PDF (682/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 18 Memory Mapping Control (S12XMMCV3)
18.4.4 Chip Bus Control
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDMand
XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus
swapping operations. All internal and external resources are connected to specific target buses (see
Figure 18-26¹).
XGATE
XGATE
DBG
CPU
S12X0
BDM
S12X1
FLEXRAY
S12X2
MMC “Crossbar Switch”
XBUS3
XBUS1
XBUS0
XRAM
XBUS2
BDM
EBI
FLFATSXH
EETX
resources
XSRAM
IPBI
Figure 18-26. MMC Block Diagram
1. Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities.
MC9S12XDP512 Data Sheet, Rev. 2.21
682
Freescale Semiconductor