MC9S12XD256MAL Datasheet, PDF (854/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.39 Port P Input Register (PTIP)
7
R PTIP7
6
PTIP6
5
PTIP5
4
PTIP4
3
PTIP3
2
PTIP2
1
PTIP1
0
PTIP0
W
Reset¹
—
—
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 22-41. Port P Input Register (PTIP)
1 _{These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated}
pin values.
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can also be used to detect
overload or short circuit conditions on output pins.
MC9S12XDP512 Data Sheet, Rev. 2.21
856
Freescale Semiconductor